Test Z6.3+poxxs

AArch64 Z6.3+poxxs
"PodWWXX WseXX PodWWXX RfeXX PodRRXX FreXX"
Cycle=RfeXX PodRRXX FreXX PodWWXX WseXX PodWWXX
Relax=
Safe=PodWW PodRR RfeXX FreXX WseXX
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=T
Com=Ws Rf Fr
Orig=PodWWXX WseXX PodWWXX RfeXX PodRRXX FreXX
{ ok=1;
0:X0=x; 0:X4=y; 0:X8=ok;
1:X0=y; 1:X4=z; 1:X8=ok;
2:X0=z; 2:X3=x; 2:X6=ok;
}
 P0              | P1              | P2              ;
 MOV W1,#1       | MOV W1,#2       | LDXR W1,[X0]    ;
 LDXR W2,[X0]    | LDXR W2,[X0]    | STXR W2,W1,[X0] ;
 STXR W3,W1,[X0] | STXR W3,W1,[X0] | CBNZ W2,Fail2   ;
 CBNZ W3,Fail0   | CBNZ W3,Fail1   | LDXR W4,[X3]    ;
 MOV W5,#1       | MOV W5,#1       | STXR W2,W4,[X3] ;
 LDXR W6,[X4]    | LDXR W6,[X4]    | CBNZ W2,Fail2   ;
 STXR W3,W5,[X4] | STXR W3,W5,[X4] | B Exit2         ;
 CBNZ W3,Fail0   | CBNZ W3,Fail1   | Fail2:          ;
 B Exit0         | B Exit1         | MOV W5,#0       ;
 Fail0:          | Fail1:          | STR W5,[X6]     ;
 MOV W7,#0       | MOV W7,#0       | Exit2:          ;
 STR W7,[X8]     | STR W7,[X8]     |                 ;
 Exit0:          | Exit1:          |                 ;
Observed
    z=1; y=2; x=1; ok=1; 2:X4=0; 2:X1=1; 1:X6=0; 1:X2=1; 0:X6=0; 0:X2=0;