Test WRR+2W+poxxs+X

AArch64 WRR+2W+poxxs+X
"RfeXX PodRRXX FreXX PodWWXX WseXX"
Cycle=RfeXX PodRRXX FreXX PodWWXX WseXX
Relax=
Safe=PodWW PodRR RfeXX FreXX WseXX
Prefetch=1:x=F,1:y=T,2:y=F,2:x=W
Com=Rf Fr Ws
Orig=RfeXX PodRRXX FreXX PodWWXX WseXX
{ ok=1;
0:X0=x; 0:X5=ok;
1:X0=x; 1:X3=y; 1:X6=ok;
2:X0=y; 2:X4=x; 2:X8=ok;
}
 P0              | P1              | P2              ;
 MOV W1,#2       | LDXR W1,[X0]    | MOV W1,#1       ;
 LDXR W2,[X0]    | STXR W2,W1,[X0] | LDXR W2,[X0]    ;
 STXR W3,W1,[X0] | CBNZ W2,Fail1   | STXR W3,W1,[X0] ;
 CBNZ W3,Fail0   | LDXR W4,[X3]    | CBNZ W3,Fail2   ;
 B Exit0         | STXR W2,W4,[X3] | MOV W5,#1       ;
 Fail0:          | CBNZ W2,Fail1   | LDXR W6,[X4]    ;
 MOV W4,#0       | B Exit1         | STXR W3,W5,[X4] ;
 STR W4,[X5]     | Fail1:          | CBNZ W3,Fail2   ;
 Exit0:          | MOV W5,#0       | B Exit2         ;
                 | STR W5,[X6]     | Fail2:          ;
                 | Exit1:          | MOV W7,#0       ;
                 |                 | STR W7,[X8]     ;
                 |                 | Exit2:          ;
Observed
    y=1; x=2; ok=1; 2:X6=0; 2:X2=0; 1:X4=0; 1:X1=2; 0:X2=1;
and y=1; x=2; ok=1; 2:X6=0; 2:X2=0; 1:X4=0; 1:X1=1; 0:X2=1;
and y=1; x=1; ok=1; 2:X6=2; 2:X2=0; 1:X4=0; 1:X1=1; 0:X2=0;