Test WRC+dmb.sys+pos

AArch64 WRC+dmb.sys+pos
"Rfe DMB.SYsRW Rfe PosRR Fre"
Cycle=Rfe PosRR Fre Rfe DMB.SYsRW
Relax=
Safe=Rfe Fre PosRR DMB.SYsRW
Prefetch=
Com=Rf Rf Fr
Orig=Rfe DMB.SYsRW Rfe PosRR Fre
{
0:X1=x;
1:X1=x;
2:X1=x;
}
 P0          | P1          | P2          ;
 MOV W0,#1   | LDR W0,[X1] | LDR W0,[X1] ;
 STR W0,[X1] | DMB SY      | LDR W2,[X1] ;
             | MOV W2,#2   |             ;
             | STR W2,[X1] |             ;
Observed
    x=2; 2:X2=0; 2:X0=2; 1:X0=1;
and x=2; 2:X2=0; 2:X0=1; 1:X0=1;
and x=2; 2:X2=0; 2:X0=2; 1:X0=0;
and x=1; 2:X2=0; 2:X0=2; 1:X0=0;
and x=1; 2:X2=2; 2:X0=1; 1:X0=0;
and x=2; 2:X2=0; 2:X0=1; 1:X0=0;
and x=1; 2:X2=0; 2:X0=1; 1:X0=0;