Test MP+dmb.sy+pos-addr-addr-rfi-ctrlisb

AArch64 MP+dmb.sy+pos-addr-addr-rfi-ctrlisb
"DMB.SYdWW Rfe PosRR DpAddrdR DpAddrdW Rfi DpCtrlIsbdR Fre"
Cycle=Rfi DpCtrlIsbdR Fre DMB.SYdWW Rfe PosRR DpAddrdR DpAddrdW
Relax=
Safe=Rfi Rfe Fre PosRR DMB.SYdWW DpAddrdW DpAddrdR DpCtrlIsbdR
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=DMB.SYdWW Rfe PosRR DpAddrdR DpAddrdW Rfi DpCtrlIsbdR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X5=z; 1:X8=a; 1:X11=x;
}
 P0          | P1                  ;
 MOV W0,#1   | LDR W0,[X1]         ;
 STR W0,[X1] | LDR W2,[X1]         ;
 DMB SY      | EOR W3,W2,W2        ;
 MOV W2,#1   | LDR W4,[X5,W3,SXTW] ;
 STR W2,[X3] | EOR W6,W4,W4        ;
             | MOV W7,#1           ;
             | STR W7,[X8,W6,SXTW] ;
             | LDR W9,[X8]         ;
             | CBNZ W9,LC00        ;
             | LC00:               ;
             | ISB                 ;
             | LDR W10,[X11]       ;
Observed
    y=1; x=1; a=1; 1:X9=1; 1:X2=0; 1:X10=1; 1:X0=1;