AArch64 SB+XALs "PodWRXALP FrePXAL PodWRXALP FrePXAL" Cycle=FrePXAL PodWRXALP FrePXAL PodWRXALP Generator=diyone7 (version 7.56+02~dev) Prefetch=0:x=F,0:y=T,1:y=F,1:x=T Com=Fr Fr Orig=PodWRXALP FrePXAL PodWRXALP FrePXAL { 0:X0=x; 0:X5=y; 0:X7=ok0; 1:X0=y; 1:X5=x; 1:X7=ok1; } P0 | P1 ; MOV W1,#1 | MOV W1,#1 ; LDAXR W2,[X0] | LDAXR W2,[X0] ; STLXR W3,W1,[X0] | STLXR W3,W1,[X0] ; CBNZ W3,End0 | CBNZ W3,End1 ; ADD W4,W4,#1 | ADD W4,W4,#1 ; LDR W6,[X5] | LDR W6,[X5] ; End0: | End1: ; STR W4,[X7] | STR W4,[X7] ; exists (x=1 /\ y=1 /\ 0:X6=0 /\ 1:X6=0 /\ ok1=1 /\ ok0=1)