Test MP+poxx+po+SYS2

AArch64 MP+poxx+po+SYS2
"PodWWXX RfeXP PodRR FrePX"
Cycle=PodRR FrePX PodWWXX RfeXP
Relax=FrePX RfeXP
Safe=PodWW PodRR
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=PodWWXX RfeXP PodRR FrePX
{
0:X0=x; 0:X4=y;
1:X1=y; 1:X3=x;
}
 P0              | P1          ;
 MOV W1,#1       | LDR W0,[X1] ;
 LDXR W2,[X0]    | LDR W2,[X3] ;
 STXR W3,W1,[X0] |             ;
 MOV W5,#1       |             ;
 LDXR W6,[X4]    |             ;
 STXR W7,W5,[X4] |             ;
exists
(x=1 /\ y=1 /\ 0:X7=0 /\ 0:X3=0 /\ 0:X2=0 /\ 0:X6=0 /\ 1:X0=1 /\ 1:X2=0)