Test MP+poll+popa

AArch64 MP+poll+popa
"PodWWLL RfeLP PodRRPA FreAL"
Cycle=RfeLP PodRRPA FreAL PodWWLL
Relax=
Safe=PodWW PodRR FreAL RfeLP
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=PodWWLL RfeLP PodRRPA FreAL
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=x;
}
 P0           | P1           ;
 MOV W0,#1    | LDR W0,[X1]  ;
 STLR W0,[X1] | LDAR W2,[X3] ;
 MOV W2,#1    |              ;
 STLR W2,[X3] |              ;
exists
(1:X0=1 /\ 1:X2=0)