Test MP+dmb.st+popl-rfilp-addr

AArch64 MP+dmb.st+popl-rfilp-addr
"DMB.SYdWW Rfe PodRWPL RfiLP DpAddrdR Fre"
Cycle=Rfe PodRWPL RfiLP DpAddrdR Fre DMB.SYdWW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=DMB.SYdWW Rfe PodRWPL RfiLP DpAddrdR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=z; 1:X7=x;
}
 P0          | P1                  ;
 MOV W0,#1   | LDR W0,[X1]         ;
 STR W0,[X1] | MOV W2,#1           ;
 DMB SY      | STLR W2,[X3]        ;
 MOV W2,#1   | LDR W4,[X3]         ;
 STR W2,[X3] | EOR W5,W4,W4        ;
             | LDR W6,[X7,W5,SXTW] ;
exists
(1:X0=1 /\ 1:X4=1 /\ 1:X6=0)