Test LB+poxxs+SYS2

AArch64 LB+poxxs+SYS2
"PodRWXX RfeXX PodRWXX RfeXX"
Cycle=RfeXX PodRWXX RfeXX PodRWXX
Relax=RfeXX
Safe=PodRW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Rf
Orig=PodRWXX RfeXX PodRWXX RfeXX
{
0:X0=x; 0:X3=y;
1:X0=y; 1:X3=x;
}
 P0              | P1              ;
 LDXR W1,[X0]    | LDXR W1,[X0]    ;
 STXR W2,W1,[X0] | STXR W2,W1,[X0] ;
 MOV W4,#1       | MOV W4,#1       ;
 LDXR W5,[X3]    | LDXR W5,[X3]    ;
 STXR W6,W4,[X3] | STXR W6,W4,[X3] ;
exists
(x=1 /\ y=1 /\ 0:X6=0 /\ 0:X2=0 /\ 0:X1=1 /\ 0:X5=0 /\ 1:X6=0 /\ 1:X2=0 /\ 1:X1=1 /\ 1:X5=0)