Test LB+po+popx+SYS2

AArch64 LB+po+popx+SYS2
"PodRW Rfe PodRWPX RfeXP"
Cycle=Rfe PodRWPX RfeXP PodRW
Relax=RfeXP
Safe=Rfe PodRW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Rf
Orig=PodRW Rfe PodRWPX RfeXP
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X2=x;
}
 P0          | P1              ;
 LDR W0,[X1] | LDR W0,[X1]     ;
 MOV W2,#1   | MOV W3,#1       ;
 STR W2,[X3] | LDXR W4,[X2]    ;
             | STXR W5,W3,[X2] ;
exists
(x=1 /\ 0:X0=1 /\ 1:X5=0 /\ 1:X0=1 /\ 1:X4=0)