AArch64 ARMARM06 "RfeLA PodRRAA FreAL RfeLA PodRRAA FreAL" Prefetch=1:x=F,1:y=T,3:y=F,3:x=T Com=Rf Fr Rf Fr Orig=RfeLA PodRRAA FreAL RfeLA PodRRAA FreAL { 0:X1=x; 1:X1=x; 1:X3=y; 2:X1=y; 3:X1=y; 3:X3=x; } P0 | P1 | P2 | P3 ; MOV W0,#1 | LDAR W0,[X1] | MOV W0,#1 | LDAR W0,[X1] ; STLR W0,[X1] | LDAR W2,[X3] | STLR W0,[X1] | LDAR W2,[X3] ; ~exists (1:X0=1 /\ 1:X2=0 /\ 3:X0=1 /\ 3:X2=0) (* ARM ARM F.2.4, basically IRIW+poaas+LL *)