Test SB+dmb.st+po

AArch64 SB+dmb.st+po
"DMB.STdWR Fre PodWR Fre"
Cycle=Fre PodWR Fre DMB.STdWR
Relax=
Safe=Fre PodWR DMB.STdWR
Prefetch=0:x=F,0:y=T,1:y=F,1:x=T
Com=Fr Fr
Orig=DMB.STdWR Fre PodWR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=x;
}
 P0          | P1          ;
 MOV W0,#1   | MOV W0,#1   ;
 STR W0,[X1] | STR W0,[X1] ;
 DMB ST      | LDR W2,[X3] ;
 LDR W2,[X3] |             ;
exists
(0:X2=0 /\ 1:X2=0)