Test MP+po+dmb.ld

AArch64 MP+po+dmb.ld
"PodWW Rfe DMB.LDdRR Fre"
Cycle=Rfe DMB.LDdRR Fre PodWW
Relax=
Safe=Rfe Fre PodWW DMB.LDdRR
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=PodWW Rfe DMB.LDdRR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=x;
}
 P0          | P1          ;
 MOV W0,#1   | LDR W0,[X1] ;
 STR W0,[X1] | DMB LD      ;
 MOV W2,#1   | LDR W2,[X3] ;
 STR W2,[X3] |             ;
exists
(1:X0=1 /\ 1:X2=0)