Test WRR+2W+dmb.sy+poll

AArch64 WRR+2W+dmb.sy+poll
"Rfe DMB.SYdRR FrePL PodWWLL WseLP"
Cycle=Rfe DMB.SYdRR FrePL PodWWLL WseLP
Relax=PodWWLL
Safe=Rfe Fre Wse DMB.SYdRR
Prefetch=1:x=F,1:y=T,2:y=F,2:x=W
Com=Rf Fr Ws
Orig=Rfe DMB.SYdRR FrePL PodWWLL WseLP
{
0:X1=x;
1:X1=x; 1:X3=y;
2:X1=y; 2:X3=x;
}
 P0          | P1          | P2           ;
 MOV W0,#2   | LDR W0,[X1] | MOV W0,#1    ;
 STR W0,[X1] | DMB SY      | STLR W0,[X1] ;
             | LDR W2,[X3] | MOV W2,#1    ;
             |             | STLR W2,[X3] ;
exists
(x=2 /\ 1:X0=2 /\ 1:X2=0)