Test W+RWC+dmb.sy+poaa+pola

AArch64 W+RWC+dmb.sy+poaa+pola
"DMB.SYdWW RfePA PodRRAA FreAL PodWRLA FreAP"
Cycle=DMB.SYdWW RfePA PodRRAA FreAL PodWRLA FreAP
Relax=PodRRAA PodWRLA
Safe=Rfe Fre DMB.SYdWW
Prefetch=0:x=F,0:y=W,1:y=F,1:z=T,2:z=F,2:x=T
Com=Rf Fr Fr
Orig=DMB.SYdWW RfePA PodRRAA FreAL PodWRLA FreAP
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=z;
2:X1=z; 2:X3=x;
}
 P0          | P1           | P2           ;
 MOV W0,#1   | LDAR W0,[X1] | MOV W0,#1    ;
 STR W0,[X1] | LDAR W2,[X3] | STLR W0,[X1] ;
 DMB SY      |              | LDAR W2,[X3] ;
 MOV W2,#1   |              |              ;
 STR W2,[X3] |              |              ;
exists
(1:X0=1 /\ 1:X2=0 /\ 2:X2=0)