Test RWC+poaa+dmb.sy+L

AArch64 RWC+poaa+dmb.sy+L
"RfeLA PodRRAA FreAP DMB.SYdWR FrePL"
Cycle=DMB.SYdWR FrePL RfeLA PodRRAA FreAP
Relax=PodRRAA
Safe=Fre DMB.SYdWR [FrePL,RfeLP]
Prefetch=1:x=F,1:y=T,2:y=F,2:x=T
Com=Rf Fr Fr
Orig=RfeLA PodRRAA FreAP DMB.SYdWR FrePL
{
0:X1=x;
1:X1=x; 1:X3=y;
2:X1=y; 2:X3=x;
}
 P0           | P1           | P2          ;
 MOV W0,#1    | LDAR W0,[X1] | MOV W0,#1   ;
 STLR W0,[X1] | LDAR W2,[X3] | STR W0,[X1] ;
              |              | DMB SY      ;
              |              | LDR W2,[X3] ;
exists
(1:X0=1 /\ 1:X2=0 /\ 2:X2=0)