Test RWC+dmb.sy+pola

AArch64 RWC+dmb.sy+pola
"Rfe DMB.SYdRR FrePL PodWRLA FreAP"
Cycle=Rfe DMB.SYdRR FrePL PodWRLA FreAP
Relax=PodWRLA
Safe=Rfe Fre DMB.SYdRR
Prefetch=1:x=F,1:y=T,2:y=F,2:x=T
Com=Rf Fr Fr
Orig=Rfe DMB.SYdRR FrePL PodWRLA FreAP
{
0:X1=x;
1:X1=x; 1:X3=y;
2:X1=y; 2:X3=x;
}
 P0          | P1          | P2           ;
 MOV W0,#1   | LDR W0,[X1] | MOV W0,#1    ;
 STR W0,[X1] | DMB SY      | STLR W0,[X1] ;
             | LDR W2,[X3] | LDAR W2,[X3] ;
exists
(1:X0=1 /\ 1:X2=0 /\ 2:X2=0)