AArch64 IRRWIW+dmb.sy+poal+LL
"RfeLP DMB.SYdRR FrePL RfeLA PodRWAL WseLL"
Cycle=DMB.SYdRR FrePL RfeLA PodRWAL WseLL RfeLP
Relax=PodRWAL
Safe=DMB.SYdRR [FrePL,RfeLP] [WsePL,RfeLP]
Prefetch=1:x=F,1:y=T,3:y=F,3:x=W
Com=Rf Fr Rf Ws
Orig=RfeLP DMB.SYdRR FrePL RfeLA PodRWAL WseLL
{
0:X1=x;
1:X1=x; 1:X3=y;
2:X1=y;
3:X1=y; 3:X3=x;
}
P0 | P1 | P2 | P3 ;
MOV W0,#2 | LDR W0,[X1] | MOV W0,#1 | LDAR W0,[X1] ;
STLR W0,[X1] | DMB SY | STLR W0,[X1] | MOV W2,#1 ;
| LDR W2,[X3] | | STLR W2,[X3] ;
exists
(x=2 /\ 1:X0=2 /\ 1:X2=0 /\ 3:X0=1)