Test MP+dmb.sy+addr-ctrl-pos-ctrl-pos

AArch64 MP+dmb.sy+addr-ctrl-pos-ctrl-pos
"DMB.SYdWW Rfe DpAddrdR DpCtrldR PosRR DpCtrldR PosRR Fre"
Cycle=Rfe DpAddrdR DpCtrldR PosRR DpCtrldR PosRR Fre DMB.SYdWW
Relax=
Safe=Rfe Fre PosRR DMB.SYdWW DpAddrdR DpCtrldR
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=DMB.SYdWW Rfe DpAddrdR DpCtrldR PosRR DpCtrldR PosRR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X4=z; 1:X6=a; 1:X9=x;
}
 P0          | P1                  ;
 MOV W0,#1   | LDR W0,[X1]         ;
 STR W0,[X1] | EOR W2,W0,W0        ;
 DMB SY      | LDR W3,[X4,W2,SXTW] ;
 MOV W2,#1   | CBNZ W3,LC00        ;
 STR W2,[X3] | LC00:               ;
             | LDR W5,[X6]         ;
             | LDR W7,[X6]         ;
             | CBNZ W7,LC01        ;
             | LC01:               ;
             | LDR W8,[X9]         ;
             | LDR W10,[X9]        ;
Observed
    y=1; x=1; 1:X8=1; 1:X10=0; 1:X0=1;
and y=1; x=1; 1:X8=1; 1:X10=0; 1:X0=0;