Test WWC+dmb.st+addr

AArch64 WWC+dmb.st+addr
"Rfe DMB.STdRW Rfe DpAddrdW Wse"
Cycle=Rfe DMB.STdRW Rfe DpAddrdW Wse
Relax=
Safe=Rfe Wse DMB.STdRW DpAddrdW
Prefetch=1:x=F,1:y=W,2:y=F,2:x=W
Com=Rf Rf Ws
Orig=Rfe DMB.STdRW Rfe DpAddrdW Wse
{
0:X1=x;
1:X1=x; 1:X3=y;
2:X1=y; 2:X4=x;
}
 P0          | P1          | P2                  ;
 MOV W0,#2   | LDR W0,[X1] | LDR W0,[X1]         ;
 STR W0,[X1] | DMB ST      | EOR W2,W0,W0        ;
             | MOV W2,#1   | MOV W3,#1           ;
             | STR W2,[X3] | STR W3,[X4,W2,SXTW] ;
Observed
    x=2; 2:X0=1; 1:X0=2;