Test S+dmb.syll+dmb.st

AArch64 S+dmb.syll+dmb.st
"DMB.SYdWWLL RfeLP DMB.STdRW WsePL"
Cycle=RfeLP DMB.STdRW WsePL DMB.SYdWWLL
Relax=
Safe=DMB.STdRW DMB.SYdWW WsePL RfeLP
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Ws
Orig=DMB.SYdWWLL RfeLP DMB.STdRW WsePL
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=x;
}
 P0           | P1          ;
 MOV W0,#2    | LDR W0,[X1] ;
 STLR W0,[X1] | DMB ST      ;
 DMB SY       | MOV W2,#1   ;
 MOV W2,#1    | STR W2,[X3] ;
 STLR W2,[X3] |             ;
Observed
    x=2; 1:X0=1;