Test LB+dmb.st+popl

AArch64 LB+dmb.st+popl
"DMB.STdRW Rfe PodRWPL RfeLP"
Cycle=Rfe PodRWPL RfeLP DMB.STdRW
Relax=
Safe=Rfe PodRW DMB.STdRW RfeLP
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Rf
Orig=DMB.STdRW Rfe PodRWPL RfeLP
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=x;
}
 P0          | P1           ;
 LDR W0,[X1] | LDR W0,[X1]  ;
 DMB ST      | MOV W2,#1    ;
 MOV W2,#1   | STLR W2,[X3] ;
 STR W2,[X3] |              ;
Observed
    1:X0=1; 0:X0=1;