Test ISA2+dmb.st+dmb.st+dmb.ld

AArch64 ISA2+dmb.st+dmb.st+dmb.ld
"DMB.STdWW Rfe DMB.STdRW Rfe DMB.LDdRR Fre"
Cycle=Rfe DMB.LDdRR Fre DMB.STdWW Rfe DMB.STdRW
Relax=
Safe=Rfe Fre DMB.LDdRR DMB.STdWW DMB.STdRW
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=T
Com=Rf Rf Fr
Orig=DMB.STdWW Rfe DMB.STdRW Rfe DMB.LDdRR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=z;
2:X1=z; 2:X3=x;
}
 P0          | P1          | P2          ;
 MOV W0,#1   | LDR W0,[X1] | LDR W0,[X1] ;
 STR W0,[X1] | DMB ST      | DMB LD      ;
 DMB ST      | MOV W2,#1   | LDR W2,[X3] ;
 MOV W2,#1   | STR W2,[X3] |             ;
 STR W2,[X3] |             |             ;
Observed
    2:X2=0; 2:X0=1; 1:X0=1;