AArch64 3.LB+dmb.st+dmb.sy+addr
"DMB.STdRW Rfe DMB.SYdRW Rfe DpAddrdW Rfe"
Cycle=Rfe DMB.STdRW Rfe DMB.SYdRW Rfe DpAddrdW
Relax=
Safe=Rfe DMB.STdRW DMB.SYdRW DpAddrdW
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=W
Com=Rf Rf Rf
Orig=DMB.STdRW Rfe DMB.SYdRW Rfe DpAddrdW Rfe
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=z;
2:X1=z; 2:X4=x;
}
P0 | P1 | P2 ;
LDR W0,[X1] | LDR W0,[X1] | LDR W0,[X1] ;
DMB ST | DMB SY | EOR W2,W0,W0 ;
MOV W2,#1 | MOV W2,#1 | MOV W3,#1 ;
STR W2,[X3] | STR W2,[X3] | STR W3,[X4,W2,SXTW] ;
Observed
2:X0=1; 1:X0=1; 0:X0=1;