AArch64 3.LB+dmb.st+ctrl+ctrlisb "DMB.STdRW Rfe DpCtrldW Rfe DpCtrlIsbdW Rfe" Cycle=Rfe DMB.STdRW Rfe DpCtrldW Rfe DpCtrlIsbdW Relax= Safe=Rfe DMB.STdRW DpCtrldW DpCtrlIsbdW Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=W Com=Rf Rf Rf Orig=DMB.STdRW Rfe DpCtrldW Rfe DpCtrlIsbdW Rfe { 0:X1=x; 0:X3=y; 1:X1=y; 1:X3=z; 2:X1=z; 2:X3=x; } P0 | P1 | P2 ; LDR W0,[X1] | LDR W0,[X1] | LDR W0,[X1] ; DMB ST | CBNZ W0,LC00 | CBNZ W0,LC01 ; MOV W2,#1 | LC00: | LC01: ; STR W2,[X3] | MOV W2,#1 | ISB ; | STR W2,[X3] | MOV W2,#1 ; | | STR W2,[X3] ; Observed 2:X0=1; 1:X0=1; 0:X0=1;