Test 3.LB+dmb.st+addr+data

AArch64 3.LB+dmb.st+addr+data
"DMB.STdRW Rfe DpAddrdW Rfe DpDatadW Rfe"
Cycle=Rfe DMB.STdRW Rfe DpAddrdW Rfe DpDatadW
Relax=
Safe=Rfe DMB.STdRW DpAddrdW DpDatadW
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=W
Com=Rf Rf Rf
Orig=DMB.STdRW Rfe DpAddrdW Rfe DpDatadW Rfe
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X4=z;
2:X1=z; 2:X3=x;
}
 P0          | P1                  | P2           ;
 LDR W0,[X1] | LDR W0,[X1]         | LDR W0,[X1]  ;
 DMB ST      | EOR W2,W0,W0        | EOR W2,W0,W0 ;
 MOV W2,#1   | MOV W3,#1           | ADD W2,W2,#1 ;
 STR W2,[X3] | STR W3,[X4,W2,SXTW] | STR W2,[X3]  ;
Observed
    2:X0=1; 1:X0=1; 0:X0=1;