Test LISA2Rei1G

LISA LISA2Rei1G
(*
 * Result: Sometimes
 *
 * One RCU grace period and two RCU read-side critical sections.
 * This would normally allow the cycle, but the first RCU read-side
 * critical section contains a memory barrier.  Unfortunately, this
 * memory barrier does not force all of the first critical section
 * to precede the grace period.  Cycle allowed.
 *)
{
x0 = 0;
x1 = 0;
x2 = 0;
}
 P0                 | P1            | P2                 ;
 f[rcu_read_lock]   | r[once] r1 x1 | f[rcu_read_lock]   ;
 w[once] x1 1       | f[sync]       | r[once] r2 x2      ;
 f[mb]              | w[once] x2 1  | w[once] x0 1       ;
 r[once] r2 x0      |               | f[rcu_read_unlock] ;
 f[rcu_read_unlock] |               |                    ;
Observed
    2:r2=1; 1:r1=1; 0:r2=1;