Test S+fencembreleaseonce+pooncerelease

C S+fencembreleaseonce+pooncerelease
Hash=c5a1f9bd2348bf7852362620cc6506f1
Cycle=RfeOnceOnce PodRWOnceRelease WseReleaseRelease FenceMbdWWReleaseOnce
Relax=WseReleaseRelease
Safe=FenceMbdWW RfeOnceOnce PodRWOnceRelease
Generator=diy7 (version 7.46+3)
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Ws
Orig=FenceMbdWWReleaseOnce RfeOnceOnce PodRWOnceRelease WseReleaseRelease

{}


P0(int* x,int* y) {
  smp_store_release(x,2);
  smp_mb();
  WRITE_ONCE(*y,1);
}

P1(int* x,int* y) {
  int r0 = READ_ONCE(*y);
  smp_store_release(x,1);
}

Observed
    x=2; 1:r0=1;

C11 equivalent:

C S+fencembreleaseonce+pooncerelease
Hash=c5a1f9bd2348bf7852362620cc6506f1
Cycle=RfeOnceOnce PodRWOnceRelease WseReleaseRelease FenceMbdWWReleaseOnce
Relax=WseReleaseRelease
Safe=FenceMbdWW RfeOnceOnce PodRWOnceRelease
Generator=diy7 (version 7.46+3)
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Ws
Orig=FenceMbdWWReleaseOnce RfeOnceOnce PodRWOnceRelease WseReleaseRelease

{}


P0(atomic_int* x,atomic_int* y) {
  atomic_store_explicit(x,2,memory_order_release);
  atomic_thread_fence(memory_order_seq_cst);
  atomic_store_explicit(y,1,memory_order_relaxed);
}

P1(atomic_int* x,atomic_int* y) {
  int r0 = atomic_load_explicit(y,memory_order_relaxed);
  atomic_store_explicit(x,1,memory_order_release);
}

exists (x=2 /\ 1:r0=1)