Test IRRWIW+fencembacquireonces+OnceRelease

C IRRWIW+fencembacquireonces+OnceRelease
Hash=51eafee5d559c30a477fc7cda282b72e
Cycle=FenceMbdRWAcquireOnce WseOnceOnce RfeOnceAcquire FenceMbdRRAcquireOnce FreOnceRelease RfeReleaseAcquire
Relax=RfeOnceAcquire FreOnceRelease RfeReleaseAcquire
Safe=FenceMbdRW FenceMbdRR WseOnceOnce
Generator=diy7 (version 7.46+3)
Prefetch=1:x=F,1:y=T,3:y=F,3:x=W
Com=Rf Fr Rf Ws
Orig=RfeOnceAcquire FenceMbdRRAcquireOnce FreOnceRelease RfeReleaseAcquire FenceMbdRWAcquireOnce WseOnceOnce

{}


P0(int* x) {
  WRITE_ONCE(*x,2);
}

P1(int* x,int* y) {
  int r0 = smp_load_acquire(x);
  smp_mb();
  int r1 = READ_ONCE(*y);
}

P2(int* y) {
  smp_store_release(y,1);
}

P3(int* x,int* y) {
  int r0 = smp_load_acquire(y);
  smp_mb();
  WRITE_ONCE(*x,1);
}

Observed
    x=2; 3:r0=1; 1:r1=0; 1:r0=2;

C11 equivalent:

C IRRWIW+fencembacquireonces+OnceRelease
Hash=51eafee5d559c30a477fc7cda282b72e
Cycle=FenceMbdRWAcquireOnce WseOnceOnce RfeOnceAcquire FenceMbdRRAcquireOnce FreOnceRelease RfeReleaseAcquire
Relax=RfeOnceAcquire FreOnceRelease RfeReleaseAcquire
Safe=FenceMbdRW FenceMbdRR WseOnceOnce
Generator=diy7 (version 7.46+3)
Prefetch=1:x=F,1:y=T,3:y=F,3:x=W
Com=Rf Fr Rf Ws
Orig=RfeOnceAcquire FenceMbdRRAcquireOnce FreOnceRelease RfeReleaseAcquire FenceMbdRWAcquireOnce WseOnceOnce

{}


P0(atomic_int* x) {
  atomic_store_explicit(x,2,memory_order_relaxed);
}

P1(atomic_int* x,atomic_int* y) {
  int r0 = atomic_load_explicit(x,memory_order_acquire);
  atomic_thread_fence(memory_order_seq_cst);
  int r1 = atomic_load_explicit(y,memory_order_relaxed);
}

P2(atomic_int* y) {
  atomic_store_explicit(y,1,memory_order_release);
}

P3(atomic_int* x,atomic_int* y) {
  int r0 = atomic_load_explicit(y,memory_order_acquire);
  atomic_thread_fence(memory_order_seq_cst);
  atomic_store_explicit(x,1,memory_order_relaxed);
}

exists (x=2 /\ 1:r0=2 /\ 1:r1=0 /\ 3:r0=1)