Test IRIW+fencembacquireonces+OnceOnce

C IRIW+fencembacquireonces+OnceOnce
Hash=fba4f7149ff6312933f1d32df950a589
Cycle=FenceMbdRRAcquireOnce FreOnceOnce RfeOnceAcquire FenceMbdRRAcquireOnce FreOnceOnce RfeOnceAcquire
Relax=RfeOnceAcquire
Safe=FenceMbdRR FreOnceOnce
Generator=diy7 (version 7.46+3)
Prefetch=1:x=F,1:y=T,3:y=F,3:x=T
Com=Rf Fr Rf Fr
Orig=RfeOnceAcquire FenceMbdRRAcquireOnce FreOnceOnce RfeOnceAcquire FenceMbdRRAcquireOnce FreOnceOnce

{}


P0(int* x) {
  WRITE_ONCE(*x,1);
}

P1(int* x,int* y) {
  int r0 = smp_load_acquire(x);
  smp_mb();
  int r1 = READ_ONCE(*y);
}

P2(int* y) {
  WRITE_ONCE(*y,1);
}

P3(int* x,int* y) {
  int r0 = smp_load_acquire(y);
  smp_mb();
  int r1 = READ_ONCE(*x);
}

Observed
    3:r1=0; 3:r0=1; 1:r1=0; 1:r0=1;

C11 equivalent:

C IRIW+fencembacquireonces+OnceOnce
Hash=fba4f7149ff6312933f1d32df950a589
Cycle=FenceMbdRRAcquireOnce FreOnceOnce RfeOnceAcquire FenceMbdRRAcquireOnce FreOnceOnce RfeOnceAcquire
Relax=RfeOnceAcquire
Safe=FenceMbdRR FreOnceOnce
Generator=diy7 (version 7.46+3)
Prefetch=1:x=F,1:y=T,3:y=F,3:x=T
Com=Rf Fr Rf Fr
Orig=RfeOnceAcquire FenceMbdRRAcquireOnce FreOnceOnce RfeOnceAcquire FenceMbdRRAcquireOnce FreOnceOnce

{}


P0(atomic_int* x) {
  atomic_store_explicit(x,1,memory_order_relaxed);
}

P1(atomic_int* x,atomic_int* y) {
  int r0 = atomic_load_explicit(x,memory_order_acquire);
  atomic_thread_fence(memory_order_seq_cst);
  int r1 = atomic_load_explicit(y,memory_order_relaxed);
}

P2(atomic_int* y) {
  atomic_store_explicit(y,1,memory_order_relaxed);
}

P3(atomic_int* x,atomic_int* y) {
  int r0 = atomic_load_explicit(y,memory_order_acquire);
  atomic_thread_fence(memory_order_seq_cst);
  int r1 = atomic_load_explicit(x,memory_order_relaxed);
}

exists (1:r0=1 /\ 1:r1=0 /\ 3:r0=1 /\ 3:r1=0)