Test WRW+WR+fencembs

C WRW+WR+fencembs
Hash=1da02104501b6f785ab90c96c5587d99
Cycle=Rfe FenceMbdRW Wse FenceMbdWR Fre
Relax=
Safe=Rfe Fre Wse FenceMbdWR FenceMbdRW
Generator=diy7 (version 7.46+1)
Prefetch=1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Ws Fr
Orig=Rfe FenceMbdRW Wse FenceMbdWR Fre

{}


P0(int* x) {
  WRITE_ONCE(*x,1);
}

P1(int* x,int* y) {
  int r0 = READ_ONCE(*x);
  smp_mb();
  WRITE_ONCE(*y,1);
}

P2(int* x,int* y) {
  WRITE_ONCE(*y,2);
  smp_mb();
  int r0 = READ_ONCE(*x);
}

Observed
    y=2; 2:r0=0; 1:r0=1;

C11 equivalent:

C WRW+WR+fencembs
Hash=1da02104501b6f785ab90c96c5587d99
Cycle=Rfe FenceMbdRW Wse FenceMbdWR Fre
Relax=
Safe=Rfe Fre Wse FenceMbdWR FenceMbdRW
Generator=diy7 (version 7.46+1)
Prefetch=1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Ws Fr
Orig=Rfe FenceMbdRW Wse FenceMbdWR Fre

{}


P0(atomic_int* x) {
  atomic_store_explicit(x,1,memory_order_relaxed);
}

P1(atomic_int* x,atomic_int* y) {
  int r0 = atomic_load_explicit(x,memory_order_relaxed);
  atomic_thread_fence(memory_order_seq_cst);
  atomic_store_explicit(y,1,memory_order_relaxed);
}

P2(atomic_int* x,atomic_int* y) {
  atomic_store_explicit(y,2,memory_order_relaxed);
  atomic_thread_fence(memory_order_seq_cst);
  int r0 = atomic_load_explicit(x,memory_order_relaxed);
}

exists (y=2 /\ 1:r0=1 /\ 2:r0=0)