Test posrr002

PPC posrr002
"Fre SyncdWW Rfe DpdR PosRR"
Cycle=Fre SyncdWW Rfe DpdR PosRR
Relax=PosRR
Safe=Fre DpdR BCSyncdWW
{
0:r2=y; 0:r4=x;
1:r2=x; 1:r5=y;
}
 P0           | P1            ;
 li r1,1      | lwz r1,0(r2)  ;
 stw r1,0(r2) | xor r3,r1,r1  ;
 sync         | lwzx r4,r3,r5 ;
 li r3,1      | lwz r6,0(r5)  ;
 stw r3,0(r4) |               ;
exists
(1:r1=1 /\ 1:r4=0 /\ 1:r6=0)