Test W+RW+RR+WW+RW+RR+sync+sync+lwsync+sync+lwsync

PPC W+RW+RR+WW+RW+RR+sync+sync+lwsync+sync+lwsync
"Rfe SyncdRW Rfe SyncdRR Fre LwSyncdWW Rfe SyncdRW Rfe LwSyncdRR Fre"
Cycle=Rfe SyncdRW Rfe SyncdRR Fre LwSyncdWW Rfe SyncdRW Rfe LwSyncdRR Fre
Relax=LwSyncdWW LwSyncdRR
Safe=Rfe Fre SyncdRW SyncdRR
Prefetch=0:x=T,1:x=F,1:y=W,2:y=F,2:z=T,3:z=F,3:a=W,4:a=F,4:b=W,5:b=F,5:x=T
Com=Rf Rf Fr Rf Rf Fr
Orig=Rfe SyncdRW Rfe SyncdRR Fre LwSyncdWW Rfe SyncdRW Rfe LwSyncdRR Fre
{
0:r2=x;
1:r2=x; 1:r4=y;
2:r2=y; 2:r4=z;
3:r2=z; 3:r4=a;
4:r2=a; 4:r4=b;
5:r2=b; 5:r4=x;
}
 P0           | P1           | P2           | P3           | P4           | P5           ;
 li r1,1      | lwz r1,0(r2) | lwz r1,0(r2) | li r1,1      | lwz r1,0(r2) | lwz r1,0(r2) ;
 stw r1,0(r2) | sync         | sync         | stw r1,0(r2) | sync         | lwsync       ;
              | li r3,1      | lwz r3,0(r4) | lwsync       | li r3,1      | lwz r3,0(r4) ;
              | stw r3,0(r4) |              | li r3,1      | stw r3,0(r4) |              ;
              |              |              | stw r3,0(r4) |              |              ;
exists
(1:r1=1 /\ 2:r1=1 /\ 2:r3=0 /\ 4:r1=1 /\ 5:r1=1 /\ 5:r3=0)