Test SB0024

PPC SB0024
"SyncdWR Fre PosWR DpDatadW PosWR Fre"
Cycle=Fre PosWR DpDatadW PosWR Fre SyncdWR
Relax=[Fre,SyncdWR,Fre]
Safe=PosWR DpDatadW
Prefetch=0:x=F,0:y=T,1:y=F,1:x=T
Com=Fr Fr
Orig=SyncdWR Fre PosWR DpDatadW PosWR Fre
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r5=x;
}
 P0           | P1           ;
 li r1,2      | li r1,1      ;
 stw r1,0(r2) | stw r1,0(r2) ;
 sync         | lwz r3,0(r2) ;
 lwz r3,0(r4) | xor r4,r3,r3 ;
              | addi r4,r4,1 ;
              | stw r4,0(r5) ;
              | lwz r6,0(r5) ;
exists
(x=2 /\ 0:r3=0 /\ 1:r6=1)