Test SB0012

PPC SB0012
"SyncdWR Fre PosWR DpCtrlIsyncdR Fre"
Cycle=Fre PosWR DpCtrlIsyncdR Fre SyncdWR
Relax=[Fre,SyncdWR,Fre]
Safe=PosWR DpCtrlIsyncdR
Prefetch=0:x=F,0:y=T,1:y=F,1:x=T
Com=Fr Fr
Orig=SyncdWR Fre PosWR DpCtrlIsyncdR Fre
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r5=x;
}
 P0           | P1           ;
 li r1,1      | li r1,1      ;
 stw r1,0(r2) | stw r1,0(r2) ;
 sync         | lwz r3,0(r2) ;
 lwz r3,0(r4) | cmpw r3,r3   ;
              | beq  LC00    ;
              | LC00:        ;
              | isync        ;
              | lwz r4,0(r5) ;
exists
(0:r3=0 /\ 1:r4=0)