Test S0176

PPC S0176
"LwSyncdWW Rfe DpAddrdR PosRR PodRW Wse"
Cycle=Rfe DpAddrdR PosRR PodRW Wse LwSyncdWW
Relax=[Wse,LwSyncdWW,Rfe]
Safe=PosRR PodRW DpAddrdR
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Ws
Orig=LwSyncdWW Rfe DpAddrdR PosRR PodRW Wse
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r5=z; 1:r8=x;
}
 P0           | P1            ;
 li r1,2      | lwz r1,0(r2)  ;
 stw r1,0(r2) | xor r3,r1,r1  ;
 lwsync       | lwzx r4,r3,r5 ;
 li r3,1      | lwz r6,0(r5)  ;
 stw r3,0(r4) | li r7,1       ;
              | stw r7,0(r8)  ;
exists
(x=2 /\ 1:r1=1)