Test R0002

PPC R0002
"LwSyncdWW Wse PosWR PosRR DpAddrdR Fre"
Cycle=Fre LwSyncdWW Wse PosWR PosRR DpAddrdR
Relax=[Fre,LwSyncdWW,Wse]
Safe=PosWR PosRR DpAddrdR
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Ws Fr
Orig=LwSyncdWW Wse PosWR PosRR DpAddrdR Fre
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r7=x;
}
 P0           | P1            ;
 li r1,1      | li r1,2       ;
 stw r1,0(r2) | stw r1,0(r2)  ;
 lwsync       | lwz r3,0(r2)  ;
 li r3,1      | lwz r4,0(r2)  ;
 stw r3,0(r4) | xor r5,r4,r4  ;
              | lwzx r6,r5,r7 ;
exists
(y=2 /\ 1:r6=0)