Test R0000

PPC R0000
"LwSyncdWW Wse PosWR DpAddrdR Fre"
Cycle=Fre LwSyncdWW Wse PosWR DpAddrdR
Relax=[Fre,LwSyncdWW,Wse]
Safe=PosWR DpAddrdR
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Ws Fr
Orig=LwSyncdWW Wse PosWR DpAddrdR Fre
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r6=x;
}
 P0           | P1            ;
 li r1,1      | li r1,2       ;
 stw r1,0(r2) | stw r1,0(r2)  ;
 lwsync       | lwz r3,0(r2)  ;
 li r3,1      | xor r4,r3,r3  ;
 stw r3,0(r4) | lwzx r5,r4,r6 ;
exists
(y=2 /\ 1:r5=0)