Test MP0190

PPC MP0190
"LwSyncdWW Rfe DpDatadW PosWR PodRR Fre"
Cycle=Rfe DpDatadW PosWR PodRR Fre LwSyncdWW
Relax=[Fre,LwSyncdWW,Rfe]
Safe=PosWR PodRR DpDatadW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=LwSyncdWW Rfe DpDatadW PosWR PodRR Fre
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r4=z; 1:r7=x;
}
 P0           | P1           ;
 li r1,1      | lwz r1,0(r2) ;
 stw r1,0(r2) | xor r3,r1,r1 ;
 lwsync       | addi r3,r3,1 ;
 li r3,1      | stw r3,0(r4) ;
 stw r3,0(r4) | lwz r5,0(r4) ;
              | lwz r6,0(r7) ;
exists
(1:r1=1 /\ 1:r6=0)