Test MP0157

PPC MP0157
"LwSyncdWW Rfe DpAddrdR DpAddrdW PodWR Fre"
Cycle=Rfe DpAddrdR DpAddrdW PodWR Fre LwSyncdWW
Relax=[Fre,LwSyncdWW,Rfe]
Safe=PodWR DpAddrdW DpAddrdR
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=LwSyncdWW Rfe DpAddrdR DpAddrdW PodWR Fre
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r5=z; 1:r8=a; 1:r10=x;
}
 P0           | P1            ;
 li r1,1      | lwz r1,0(r2)  ;
 stw r1,0(r2) | xor r3,r1,r1  ;
 lwsync       | lwzx r4,r3,r5 ;
 li r3,1      | xor r6,r4,r4  ;
 stw r3,0(r4) | li r7,1       ;
              | stwx r7,r6,r8 ;
              | lwz r9,0(r10) ;
exists
(1:r1=1 /\ 1:r9=0)