Test MP0144

PPC MP0144
"LwSyncdWW Rfe DpAddrdW PosWR PosRR Fre"
Cycle=Rfe DpAddrdW PosWR PosRR Fre LwSyncdWW
Relax=[Fre,LwSyncdWW,Rfe]
Safe=PosWR PosRR DpAddrdW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=LwSyncdWW Rfe DpAddrdW PosWR PosRR Fre
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r5=x;
}
 P0           | P1            ;
 li r1,2      | lwz r1,0(r2)  ;
 stw r1,0(r2) | xor r3,r1,r1  ;
 lwsync       | li r4,1       ;
 li r3,1      | stwx r4,r3,r5 ;
 stw r3,0(r4) | lwz r6,0(r5)  ;
              | lwz r7,0(r5)  ;
exists
(x=2 /\ 1:r1=1 /\ 1:r7=1)