Test MP0143

PPC MP0143
"LwSyncdWW Rfe PodRR DpAddrdR PosRR Fre"
Cycle=Rfe PodRR DpAddrdR PosRR Fre LwSyncdWW
Relax=[Fre,LwSyncdWW,Rfe]
Safe=PosRR PodRR DpAddrdR
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=LwSyncdWW Rfe PodRR DpAddrdR PosRR Fre
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r4=z; 1:r7=x;
}
 P0           | P1            ;
 li r1,1      | lwz r1,0(r2)  ;
 stw r1,0(r2) | lwz r3,0(r4)  ;
 lwsync       | xor r5,r3,r3  ;
 li r3,1      | lwzx r6,r5,r7 ;
 stw r3,0(r4) | lwz r8,0(r7)  ;
exists
(1:r1=1 /\ 1:r8=0)