Test MP0128

PPC MP0128
"LwSyncdWW Rfe PosRR DpCtrldW PosWR Fre"
Cycle=Rfe PosRR DpCtrldW PosWR Fre LwSyncdWW
Relax=[Fre,LwSyncdWW,Rfe]
Safe=PosWR PosRR DpCtrldW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=LwSyncdWW Rfe PosRR DpCtrldW PosWR Fre
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r5=x;
}
 P0           | P1           ;
 li r1,2      | lwz r1,0(r2) ;
 stw r1,0(r2) | lwz r3,0(r2) ;
 lwsync       | cmpw r3,r3   ;
 li r3,1      | beq  LC00    ;
 stw r3,0(r4) | LC00:        ;
              | li r4,1      ;
              | stw r4,0(r5) ;
              | lwz r6,0(r5) ;
exists
(x=2 /\ 1:r1=1 /\ 1:r6=1)