Test MP0112

PPC MP0112
"LwSyncdWW Rfe DpCtrldW PodWR DpCtrlIsyncdR Fre"
Cycle=Rfe DpCtrldW PodWR DpCtrlIsyncdR Fre LwSyncdWW
Relax=[Fre,LwSyncdWW,Rfe]
Safe=PodWR DpCtrldW DpCtrlIsyncdR
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=LwSyncdWW Rfe DpCtrldW PodWR DpCtrlIsyncdR Fre
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r4=z; 1:r6=a; 1:r8=x;
}
 P0           | P1           ;
 li r1,1      | lwz r1,0(r2) ;
 stw r1,0(r2) | cmpw r1,r1   ;
 lwsync       | beq  LC00    ;
 li r3,1      | LC00:        ;
 stw r3,0(r4) | li r3,1      ;
              | stw r3,0(r4) ;
              | lwz r5,0(r6) ;
              | cmpw r5,r5   ;
              | beq  LC01    ;
              | LC01:        ;
              | isync        ;
              | lwz r7,0(r8) ;
exists
(1:r1=1 /\ 1:r7=0)