Test MP0100

PPC MP0100
"LwSyncdWW Rfe PosRR DpAddrdR DpCtrlIsyncdR Fre"
Cycle=Rfe PosRR DpAddrdR DpCtrlIsyncdR Fre LwSyncdWW
Relax=[Fre,LwSyncdWW,Rfe]
Safe=PosRR DpAddrdR DpCtrlIsyncdR
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=LwSyncdWW Rfe PosRR DpAddrdR DpCtrlIsyncdR Fre
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r6=z; 1:r8=x;
}
 P0           | P1            ;
 li r1,1      | lwz r1,0(r2)  ;
 stw r1,0(r2) | lwz r3,0(r2)  ;
 lwsync       | xor r4,r3,r3  ;
 li r3,1      | lwzx r5,r4,r6 ;
 stw r3,0(r4) | cmpw r5,r5    ;
              | beq  LC00     ;
              | LC00:         ;
              | isync         ;
              | lwz r7,0(r8)  ;
exists
(1:r1=1 /\ 1:r7=0)