Test MP0093

PPC MP0093
"LwSyncdWW Rfe PosRW PodWR DpAddrdR Fre"
Cycle=Rfe PosRW PodWR DpAddrdR Fre LwSyncdWW
Relax=[Fre,LwSyncdWW,Rfe]
Safe=PosRW PodWR DpAddrdR
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=LwSyncdWW Rfe PosRW PodWR DpAddrdR Fre
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r5=z; 1:r8=x;
}
 P0           | P1            ;
 li r1,1      | lwz r1,0(r2)  ;
 stw r1,0(r2) | li r3,2       ;
 lwsync       | stw r3,0(r2)  ;
 li r3,1      | lwz r4,0(r5)  ;
 stw r3,0(r4) | xor r6,r4,r4  ;
              | lwzx r7,r6,r8 ;
exists
(y=2 /\ 1:r1=1 /\ 1:r7=0)