Test MP0018

PPC MP0018
"PodWR PosRR DpDatadW Rfe DpAddrdR Fre"
Cycle=Rfe DpAddrdR Fre PodWR PosRR DpDatadW
Relax=[Rfe,DpAddrdR,Fre]
Safe=PosRR PodWR DpDatadW
Prefetch=0:x=F,0:z=W,1:z=F,1:x=T
Com=Rf Fr
Orig=PodWR PosRR DpDatadW Rfe DpAddrdR Fre
{
0:r2=x; 0:r4=y; 0:r7=z;
1:r2=z; 1:r5=x;
}
 P0           | P1            ;
 li r1,1      | lwz r1,0(r2)  ;
 stw r1,0(r2) | xor r3,r1,r1  ;
 lwz r3,0(r4) | lwzx r4,r3,r5 ;
 lwz r5,0(r4) |               ;
 xor r6,r5,r5 |               ;
 addi r6,r6,1 |               ;
 stw r6,0(r7) |               ;
exists
(1:r1=1 /\ 1:r4=0)