Test MP+PPO902

PPC MP+PPO902
"Fre LwSyncdWW Rfe DpDatadW PosWR PosRR"
Cycle=Rfe DpDatadW PosWR PosRR Fre LwSyncdWW
Relax=
Safe=Rfe Fre PosWR PosRR LwSyncdWW DpDatadW
Prefetch=1:x=T
Com=Rf Fr
Orig=Fre LwSyncdWW Rfe DpDatadW PosWR PosRR
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r4=x;
}
 P0           | P1           ;
 li r1,2      | lwz r1,0(r2) ;
 stw r1,0(r2) | xor r3,r1,r1 ;
 lwsync       | addi r3,r3,1 ;
 li r3,1      | stw r3,0(r4) ;
 stw r3,0(r4) | lwz r5,0(r4) ;
              | lwz r6,0(r4) ;
exists
(x=2 /\ 1:r1=1 /\ 1:r6=1)