Test MP+PPO873

PPC MP+PPO873
"Fre LwSyncdWW Rfe DpAddrdR DpAddrdW PosWR PosRR"
Cycle=Rfe DpAddrdR DpAddrdW PosWR PosRR Fre LwSyncdWW
Relax=
Safe=Rfe Fre PosWR PosRR LwSyncdWW DpAddrdW DpAddrdR
Prefetch=1:x=T
Com=Rf Fr
Orig=Fre LwSyncdWW Rfe DpAddrdR DpAddrdW PosWR PosRR
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r5=z; 1:r8=x;
}
 P0           | P1            ;
 li r1,2      | lwz r1,0(r2)  ;
 stw r1,0(r2) | xor r3,r1,r1  ;
 lwsync       | lwzx r4,r3,r5 ;
 li r3,1      | xor r6,r4,r4  ;
 stw r3,0(r4) | li r7,1       ;
              | stwx r7,r6,r8 ;
              | lwz r9,0(r8)  ;
              | lwz r10,0(r8) ;
exists
(x=2 /\ 1:r1=1 /\ 1:r10=1)