Test MP+PPO824

PPC MP+PPO824
"Fre LwSyncdWW Rfe PosRR DpAddrdR DpCtrldW PosWR DpAddrdR PosRR"
Cycle=Rfe PosRR DpAddrdR DpCtrldW PosWR DpAddrdR PosRR Fre LwSyncdWW
Relax=
Safe=Rfe Fre PosWR PosRR LwSyncdWW DpAddrdR DpCtrldW
Prefetch=1:x=T
Com=Rf Fr
Orig=Fre LwSyncdWW Rfe PosRR DpAddrdR DpCtrldW PosWR DpAddrdR PosRR
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r6=z; 1:r8=a; 1:r12=x;
}
 P0           | P1               ;
 li r1,1      | lwz r1,0(r2)     ;
 stw r1,0(r2) | lwz r3,0(r2)     ;
 lwsync       | xor r4,r3,r3     ;
 li r3,1      | lwzx r5,r4,r6    ;
 stw r3,0(r4) | cmpw r5,r5       ;
              | beq  LC00        ;
              | LC00:            ;
              | li r7,1          ;
              | stw r7,0(r8)     ;
              | lwz r9,0(r8)     ;
              | xor r10,r9,r9    ;
              | lwzx r11,r10,r12 ;
              | lwz r13,0(r12)   ;
exists
(1:r1=1 /\ 1:r13=0)